Nonvolatile programmable logic switch

ABSTRACT

A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2011-207606 filed on Sep. 22, 2011in Japan, the entire contents of which are incorporated herein byreference.

FIELD

Embodiments described herein relate generally to a nonvolatileprogrammable logic switch.

BACKGROUND

A programmable logic switch is an element which controls on/off of alogic switch (for example, a transistor or the like) in accordance withdata retained in a memory. In general, the programmable logic switch isused in programmable logic devices such as an FPGA (Field ProgrammableGate Array) or the like in which a logic operational circuit or aninterconnection circuit needs to be reconfigured. For example, suchprogrammable logic device includes plural wirings and a connection unit(plural connection units) for switching connection/disconnection ofthese wirings. The programmable logic switches may be used in suchconnection unit.

In a programmable logic switch used in the FPGA, a volatile memory suchas an SRAM is used as a memory. If the power supply is turned off,therefore, data stored in the memory is lost. Therefore, there is aproblem that data must be read anew from a memory region providedseparately when the power supply is turned on again. Furthermore, ingeneral, the SRAM is formed of six transistors. Therefore, there is aproblem that the area of the chip becomes large in an FPGA which uses alarge number of SRAMs.

Schemes using a nonvolatile flash memory as a memory in the programmablelogic switch are known. In one of the schemes, one cell in theprogrammable logic switch is formed of two nonvolatile memorytransistors and one switching transistor (pass transistor). As thememory transistors, for example, flash memory transistors are used. Apower supply voltage or 0 V is input to the switching transistor at itsgate via one of the two flash memory transistors. When it is desired towrite data into the memory, a write voltage is applied to a flash memorytransistor at its gate. In general, the write voltage is approximately20 V. At this time, 0 V is applied to the memory transistor at itssource. The writing utilizes the principle called FN (Fowler-Nordheim)tunnel current, and the writing is said to be advantageous in shrinkingthe sizes of the memory transistors. In the case where the programmablelogic switch is disposed in an array form, a plurality of memorytransistors share a gate. For implementing selective writing, a writeinhibit voltage must be applied to a source of a memory transistor in anunselected cell. At this time, a conductive channel is formed in thememory transistor in the unselected cell, and the write inhibit voltageis unwillingly applied to a gate of the memory transistor in theunselected cell. In general, approximately 5 V is needed as the writeinhibit voltage. On the other hand, it is desirable to make a gateinsulation film of the switching transistor as thin as approximatelyseveral nm in order to obtain high driving force. Therefore, there is afear that the gate insulation film might be broken down by the writeinhibit voltage. If the gate insulation film of the switching transistoris made sufficiently thick, it is possible to prevent breakdown causedby the write inhibit voltage. However, the driving force of theswitching transistor gets small and the speed of the programmable logicswitch falls.

In another one of the schemes using a nonvolatile flash memory as amemory in the programmable logic switch, one cell in the programmablelogic switch is formed of two nonvolatile memory transistors, oneswitching transistor, and one access transistor. As the memorytransistors, for example, flash memory transistors are used. A powersupply voltage or 0 V is input to the switching transistor at its gatevia one of the two flash memory transistors. The two memory transistorsin the same cell share a gate electrode. When it is desired to writedata into one of the two memory transistors, a first write voltage isapplied to the common gate of the memory transistors and a second writevoltage is applied to a memory transistor into which data is to bewritten, at its source. At this time, 0 V is applied to the gate of theswitching transistor via the access transistor. As a result, the secondwrite voltage is applied between the source and drain of the memorytransistor into which data is to be written. Accordingly, selectivewriting is implemented. In this scheme, hot-electrons are used forwriting into the memory transistor. In other words, hot-electronsgenerated by a potential difference between the source and drain areimplanted into a charge trap film by the voltage applied to the gate.However, it is known that in general the generation efficiency ofhot-electrons falls if the gate length of a transistor becomes smallerthan 100 nm. Therefore, the write scheme using hot-electrons becomesdifficult because of the size shrinking of transistors. In order toimplement the writing, therefore, the ion implantation condition and thelike for the memory transistors must be restricted strictly. As aresult, the development cost therefor and a cost for holding downvariations to low values increases.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a programmable logic switchaccording to a first embodiment;

FIG. 2 is a circuit diagram showing a programmable logic switchaccording to a first example of the first embodiment;

FIGS. 3( a) and 3(b) are sectional views showing an FG transistor and aMONOS transistor, respectively;

FIG. 4 is a circuit diagram showing a programmable logic switchaccording to a second example of the first embodiment;

FIG. 5 is a circuit diagram showing a programmable logic switchaccording to a third example of the first embodiment;

FIG. 6 is a sectional view showing the programmable logic switchaccording to the third example;

FIG. 7 is a diagram for explaining a write method for a memory in thefirst embodiment;

FIG. 8 is a diagram for explaining a write preventing method for amemory in the first embodiment;

FIG. 9 is a diagram for explaining a first concrete example of an erasemethod for a memory in the first embodiment;

FIG. 10 is a diagram for explaining a second concrete example of anerase method for a memory in the first embodiment;

FIG. 11 is a diagram for explaining a third concrete example of an erasemethod for a memory in the first embodiment;

FIG. 12 is a diagram showing an example of a voltage applying conditionin a case where a programmable logic switch according to the firstembodiment is made to operate;

FIG. 13 is a diagram showing a first concrete example of a circuit in acase where logic switches according to the first embodiment are arrangedin an array form as cells;

FIG. 14 is a diagram for explaining a write method in the circuit of thefirst concrete example;

FIG. 15 is a diagram showing a second concrete example of a circuit in acase where logic switches according to the first embodiment are arrangedin an array form as cells;

FIG. 16 is a diagram for explaining a write method in the circuit of thesecond concrete example;

FIG. 17 is a circuit diagram showing a programmable logic switchaccording to a fourth example of the first embodiment;

FIG. 18 is a circuit diagram showing a programmable logic switch of afirst comparative example of the first embodiment;

FIG. 19 is a circuit diagram showing a programmable logic switch of asecond comparative example of the first embodiment;

FIG. 20 is a circuit diagram showing a programmable logic switchaccording to a second embodiment;

FIG. 21 is a circuit diagram showing a programmable logic switchaccording to a first example of the second embodiment;

FIG. 22 is a circuit diagram showing a programmable logic switchaccording to a second example of the second embodiment;

FIG. 23 is a diagram for explaining a write method for a memory in thesecond embodiment;

FIG. 24 is a diagram for explaining a write preventing method for amemory in the second embodiment;

FIG. 25 is a diagram for explaining a first concrete example of an erasemethod for a memory in the second embodiment;

FIG. 26 is a diagram for explaining a second concrete example of anerase method for a memory in the second embodiment;

FIG. 27 is a diagram for explaining a third concrete example of an erasemethod for a memory in the second embodiment;

FIG. 28 is a diagram showing an example of a voltage applying conditionin a case where a programmable logic switch according to the secondembodiment is made to operate;

FIG. 29 is a diagram showing a first concrete example of a circuit in acase where logic switches according to the second embodiment arearranged in an array form as cells;

FIG. 30 is a diagram for explaining a write method in the circuit of thefirst concrete example shown in FIG. 29;

FIG. 31 is a circuit diagram showing a programmable logic switchaccording to a third example of the second embodiment; and

FIGS. 32( a) to 32(d) are block diagrams showing an FPGA according to athird embodiment.

DETAILED DESCRIPTION

A nonvolatile programmable logic switch according to an embodimentincludes: first and second cells, each of the first and second cellscomprising: a first memory having a first terminal, a second terminal,and a third terminal which receives a control signal to control a memorystate, the first memory being a first memory transistor having a gatestructure formed by stacking a first insulation film, a charge trapfilm, a second insulation film, and a gate electrode, the source and thedrain of the first memory transistor being the first and secondterminal, and the gate electrode being the third terminal; a firsttransistor connected at one of source/drain thereof to the secondterminal; and a second transistor connected at a gate thereof to theother of the source/drain of the first transistor, the third terminal ofthe first memory in the first cell and the third terminal of the firstmemory in the second cell being connected in common, and when conductingwriting into the first memory in the first cell, the third terminalbeing connected to a write power supply which generates a write voltage,the first terminal of the first memory in the first cell being connectedto a ground power supply, and the first terminal of the first memory inthe second cell being connected to a write inhibit power supply whichgenerates a write inhibit voltage.

Hereafter, embodiments will be described with reference to the drawings.

First Embodiment

A nonvolatile programmable logic switch (hereafter referred to as logicswitch as well) according to a first embodiment is shown in FIG. 1. Thelogic switch according to the first embodiment includes memories 10 ₁and 10 ₂ each having two signal electrodes and a control electrodecapable of controlling on/off of signal transmission, a cutofftransistor 20, and a pass transistor 30. Both memories 10 ₁ and 10 ₂ areconnected to a common node 15. By the way, the memories 10 ₁ isconnected to a bit line BL1 and a word line WL1 as well, and thememories 10 ₂ is connected to a bit line BL2 and a word line WL2 aswell. The cutoff transistor 20 is a MOS transistor, one of its sourceand drain (hereafter referred to as source/drain as well) is connectedto the node 15, and the other of its source and drain is connected tothe pass transistor 30 at its gate. Furthermore, the cutoff transistor20 is connected at its gate to a control line CL.

Even if the potential on the node 15 changes in all operations, such aswrite and erase operations, of the memories 10 ₁ and 10 ₂, it ispossible in the present embodiment to intercept the potential by thecutoff transistor 20 and prevent a high voltage from being applied tothe gate of the pass transistor 30. Hereafter, a voltage applying methodin the case where flash memory transistors each having a charge trapfilm are used as the memories will be described.

First Example

A logic switch according to a first example using flash memorytransistors (referred to as memory transistors as well) as the memorytransistors 10 ₁ and 10 ₂ in the first embodiment is shown in FIG. 2.The memory transistors 10 ₁ and 10 ₂ are fabricated in the same well,and a terminal (electrode) SUB for applying a substrate voltage isprovided in this well.

The memory transistors 10 ₁ and 10 ₂ can be FG (Floating Gate)transistors using a floating gate as the charge trap film or can beMONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistors using aninsulative silicon nitride film as the charge trap film. In the casewhere the MONOS transistors are used, however, compatibility of theprocess with a logic transistor such as the pass transistor is betterand it is possible to mixedly mount the memories and a logic circuit incloser vicinity to each other and suppress the area of the chip to asmall value.

FIGS. 3( a) and 3(b) show general configurations of the FG transistorand the MONOS transistor, respectively. As shown in FIG. 3( a), the FGtransistor includes a source 10 a and a drain 10 b formed in a well 4with a distance between them, a tunnel film 10 c formed on the well 4between the source 10 a and the drain 10 b, a floating gate 10 d 1formed on the tunnel film 10 c, an inter-electrode insulation film 10 e1 formed on the floating gate 10 d 1, and a control gate 10 f formed onthe inter-electrode insulation film 10 e 1. As shown in FIG. 3( b), theMONOS transistor includes a source 10 a and a drain 10 b formed in awell 4 with a distance between them, a tunnel film 10 c formed on thewell 4 between the source 10 a and the drain 10 b, a charge trap film 10d 2 formed on the tunnel film 10 c, a block insulation film 10 e 2formed on the charge trap film 10 d 2, and a control gate 10 f formed onthe block insulation film 10 e 2.

The memory transistor 10 ₁ is connected at one of its source/drain tothe bit line BL1, connected at the other of its source/drain to the node15, and connected at its gate to the word line WL1. Furthermore, thememory transistor 10 ₂ is connected at one of its source/drain to thenode 15, connected at the other of its source/drain to the bit line BL2,and connected at its gate to the word line WL2.

Second Example

In the first example shown in FIG. 2, one cutoff transistor 20 is usedper cell. As in a second example shown in FIG. 4, however, it ispossible to use two cutoff transistors 20 ₁ and 20 ₂ and dispose onecutoff transistor 20 _(i) with respect to each memory transistor 10 _(i)(i=1, 2). In this case, the cutoff transistor 20 ₁ is connected at oneof its source/drain to the memory transistor 10 ₁ at one of itssource/drain, and the cutoff transistor 20 ₁ is connected at the otherof its source/drain to the node 15 a as shown in FIG. 4. Furthermore,the cutoff transistor 20 ₂ is connected at one of its source/drain tothe memory transistor 10 ₂ at one of its source/drain, and the cutofftransistor 20 ₂ is connected at the other of its source/drain to thenode 15 a. Moreover, the pass transistor 30 is connected at its gate tothe node 15 a. By the way, gates of the cutoff transistors 20 ₁ and 20 ₂are connected to the same control line CL.

The structure of the second example shown in FIG. 4 is a structurecommon to general NOR flash memories in that one select gate (cutofftransistor) is used for one memory transistor. Therefore, there is amerit that fabrication processes used in existing NOR flash memories canbe utilized and the development cost can be held down to a low value.

Third Example

A logic switch according to a third example is shown in FIG. 5. Thelogic switch according to the third example has a structure obtained byforming the memory transistors 10 ₁ and 10 ₂, and the cutoff transistor20 and the pass transistor 30 in different wells isolated by a deviceisolation region in the first example shown in FIG. 2. Therefore, aterminal SUB1 for applying a substrate bias is provided in a well inwhich the memory transistors 10 ₁ and 10 ₂, are formed, and a terminalSUB2 for applying a substrate bias is provided in a well in which thecutoff transistor 20 and the pass transistor 30 are formed. Owing tosuch a configuration, the substrate bias can be applied to the memorytransistors 10 ₁ and 10 ₂ independently of the cutoff transistor 20 andthe pass transistor 30.

A sectional view showing a configuration of a logic switch according tothe third example is shown in FIG. 6. In an n-well, p-wells 4 a and 4 bare formed. These p-wells 4 a and 4 b are isolated by a device isolationregion 5 a. Memory transistors 10 ₁ and 10 ₂ are formed in the p-well 4a. Furthermore, the terminal SUB1 for applying the substrate bias isprovided in the p-well 4 a. A region where the terminal SUB1 is providedis isolated from a region where the memory transistors 10 ₁ and 10 ₂ areformed by a device isolation region 5 b. Furthermore, the element regionwhere the terminal SUB1 is provided is isolated from the n-well 2 by adevice isolation region 5 c. The memory transistor 10 ₁ is connected atone of its source/drain to the bit line BL1. The other of thesource/drain of the memory transistor 10 ₁ is shared with one of thesource/drain of the memory transistor 10 ₂ and connected to the node 15.The other of the source/drain of the memory transistor 10 ₂ is connectedto the bit line BL2.

The cutoff transistor 20 and the pass transistor 30 are formed in thep-well 4 b. A region where the cutoff transistor 20 is formed isisolated from a region where the pass transistor 30 is formed, by adevice isolation region 5 d. Furthermore, the terminal SUB2 for applyingthe substrate bias is provided in the p-well 4 b. A region where theterminal SUB2 is provided is isolated from a region where the passtransistor 30 is formed, by a device isolation region 5 e. Furthermore,the p-well 4 b is isolated from the n-well 2 by an element isolationregion 5 f. The cutoff transistor 20 is connected at one of itssource/drain to the node 15, and connected at the other of itssource/drain to the gate of the pass transistor 30.

(Write Method)

A program method (write method) of a memory in the logic switchaccording to the first embodiment will now be described with referenceto FIG. 7. If it is desired to write data selectively into the memorytransistor 10 ₁, a write voltage is applied to the word line WL1. Thewrite voltage is, for example, 20 V. 0 V is applied to the word line WL2connected to the gate of the memory transistor 10 ₂ to be not writtenin. Furthermore, 0 V is applied to both the bit lines BL1 and BL2. Atthis time, a channel is formed in the memory transistor 10 ₁, andelectrons are injected from the channel into the charge trap film by anFN current. On the other hand, a channel is not formed in the memorytransistor 10 ₂, and consequently writing into the memory transistor 10₂ does not occur.

(Write Preventing Method)

In the case where a plurality of logic switches are arranged in anarray, a plurality of memory transistors share a word line. If a writevoltage 20 V is applied to a word line connected to the gate of a memorytransistor to be written in, therefore, the 20 V is also applied to agate of a memory transistor which is other than the memory transistor tobe written in and which is connected to the word line, i.e., a gate of amemory transistor to be not written in. In order to implement selectivewriting, therefore, a write inhibit voltage of 5 V is applied to the bitline BL1 connected to the memory transistor 10 ₁ to be not written in asshown in FIG. 8 and consequently unexpected writing error into a memorytransistor to be not written in is prevented. In the memory transistor10 ₁ to be not written in, the voltage of 20 V is applied to its gateand consequently a channel is formed. Since a potential on the channelis 5 V which is equal to the potential on the bit line BL1 and apotential difference between the channel and the gate is 15 V, however,writing error does not occur. At this time, the potential on the node 15is also 5 V. If the cutoff transistor 20 is brought into the off-stateby adjusting the potential on the control line CL connected to the gateof the cutoff transistor 20, however, 5 V is not applied to the gate ofthe pass transistor 30. In FIG. 8, the voltage applied to the controlline CL is 0 V. However, the voltage applied to the control line CLcannot be 0 V as long as it is lower than a threshold voltage of thecutoff transistor 20. The voltage applied to the bit line BL2 can beequal to the voltage applied to the bit line BL1, or can be 0 V. In thecase where 0 V is applied, however, the voltage applied to the word lineWL2 must be made lower than a threshold voltage of the memory transistor10 ₂. The reason is as follows: if a voltage of at least the thresholdvoltage is applied to the gate of the memory transistor 10 ₂ in a statein which there is a potential difference between the source/drain of thememory transistor 10 ₂, there is a fear that data will be written intothe memory transistor 10 ₂ by generated hot-electrons.

(Erase Method)

A method for erasing data in memories in the logic switch according tothe first embodiment in the lump will now be described with reference toFIGS. 9 to 11.

FIG. 9 shows a first concrete example of the erase method. An erasevoltage is applied to the word lines WL1 and WL2 in a state in which 0 Vis applied to the terminal SUB as the substrate bias and both potentialson the bit lines BL1 and BL2 are made to be 0 V. At this time, the erasevoltage is negative in sign and is, for example, −20 V. A secondconcrete example of the erase method is shown in FIG. 10. In the secondconcrete example of the erase method shown in FIG. 10, a positive erasevoltage of, for example, 20 V is applied to the terminal SUB in a statein which the word lines WL1 and WL2 are brought to 0 V. At this time,the bit lines BL1 and BL2 should be kept in the floating state, orshould be supplied with a voltage which is at least the voltage appliedto the terminal SUB. In the case of the second concrete example shown inFIG. 10, a negative voltage is not necessary and consequently a powersupply for negative voltage cannot be provided and an advantage that thearea can be made small is obtained. If the well for the memorytransistor is common to the well for the pass transistor, however, thesubstrate bias is output from the pass transistor 30 via thesource/drain of the pass transistor 30 by applying 20 V as the substratebias. In general, it is considered that an output of the pass transistor30 is connected to, for example, an input of an inverter. If the voltageof 20 V is applied to the input of the inverter, then a problem thatgate breakdown of the transistor in the inverter might occur is posed.This problem can be solved by adopting a configuration capable ofapplying different substrate biases to the memory transistors 10 ₁ and10 ₂ and the pass transistor 30 respectively, i.e., a configuration in athird example. If in this case, for example, the substrate bias of thepass transistor 30 is set equal to 0 V as indicated in an erase methodof a third concrete example shown in FIG. 11, the problem can be solved.

On the other hand, in the erase method in the first concrete exampleshown in FIG. 9, the substrate bias applied to the terminal SUB is setequal to 0 V and consequently a high voltage is not output from the passtransistor 30. Furthermore, even if the potential on the node 15 ismodulated in the negative direction by a negative voltage applied to theword lines WL1 and WL2, the substrate bias of 0 V is applied via thesource/drain of the memory transistors 10 ₁ and 10 ₂, and the potentialon the node 15 gets equal to 0 V swiftly.

(Operation of Logic Switch)

An example of a voltage condition in a case where the programmable logicswitch is made to operate on the basis of information written into amemory is shown in FIG. 12. It is now supposed that the memorytransistor 10 ₁ and the memory transistor 10 ₂ are programmed indifferent states, respectively. For example, if the memory transistor 10₁ is in a write state, the memory transistor 10 ₂ is in an erase state.A read voltage Vread is applied to the word lines WL1 and WL2. The readvoltage Vread is an arbitrary voltage which is greater than a thresholdvoltage of the memory transistors 10 ₁ and 10 ₂ in the erase state andwhich is less than a threshold voltage of the memory transistors 10 ₁and 10 ₂ in the write state. Furthermore, a voltage Vpass which is atleast the threshold voltage of the cutoff transistor 20 is applied tothe control line CL to electrically connect the gate of the passtransistor 30 to the node 15. As for the bit lines BL1 and BL2, thepower supply voltage VDD is applied to one of them, and 0 V is appliedto the other of them. In response to the program state of the memorytransistors, the gate of the pass transistor 30 is connected to thepower supply voltage VDD or 0 V and the pass transistor 30 is broughtinto the on-state or off-state.

In general, even if the power supply is cut off, data are not lost inthe nonvolatile programmable logic switch. Therefore, it is possible toimplement the power gating technique which reduces the power consumptionof the whole chip by cutting off the power supply for regions which arenot being used. In general, a transistor for signal interception isprovided between the power supply and the memory transistors to preventthe power supply voltage from being applied to the memory transistor. Inthis case, however, additional transistors for cutting off the powersupply are necessary.

In the first embodiment, it is possible to prevent the power supplyvoltage from being applied to the gate of the pass transistor 30 byturning off the cutoff transistor 20 in regions which are not beingused. As a result, it is possible to exclude power consumption caused bya gate leakage current of the pass transistor 30 and it becomes possibleto yield an effect equivalent to that of the power gating.

(Logic Switch Arranged in Array Form)

Concrete examples of a circuit in a case where the logic switchesaccording to the first embodiment are arranged in an array form as cellswill now be described with reference to FIGS. 13 to 16.

First Concrete Example

A first concrete example shown in FIG. 13 is a circuit in the case wherecells which are adjacent to each other in the row direction share a partof a bit line. The first concrete example shown in FIG. 13 includescells M_(ij) (i, j=1, 2) arranged in two rows by two columns. Forexample, a cell M₁₁ and a cell M₁₂ are cells which are adjacent to eachother in the row direction, and the cells M₁₁ and M₁₂ share the bit lineBL2. By the way, each cell is, for example, the logic switch in thefirst example shown in FIG. 2.

In the cells M₁₁ and M₁₂ in a first row, the memory transistor 10 ₁ isconnected at its gate to the word line WL1, the memory transistor 10 ₂is connected at its gate to the word line WL2, and the cutoff transistor20 is connected at its gate to a control line CL1.

In the cells M₂₁ and M₂₂ in a second row, the memory transistor 10 ₁ isconnected at its gate to a word line WL3, the memory transistor 10 ₂ isconnected at its gate to a word line WL4, and the cutoff transistor 20is connected at its gate to a control line CL2.

In the cells M₁₁ and M₂₁ in a first column, the memory transistors 10 ₁and 10 ₂ are connected at one of its source/drain to the bit lines BL1and BL2, respectively. Furthermore, the path transistor 30 is connectedat one of its source/drain to an interconnection Y1 disposed in thecolumn direction, and connected at the other of its source/drain to aninterconnection X1 or an interconnection X2 disposed in the rowdirection.

In the cells M₁₂ and M₂₂ in a second column, the memory transistors 10 ₁and 10 ₂ are connected at one of its source/drain to the bit lines BL2and BL3, respectively. Furthermore, the path transistor 30 is connectedat one of its source/drain to an interconnection Y2 disposed in thecolumn direction, and connected at the other of its source/drain to theinterconnection X1 or the interconnection X2 disposed in the rowdirection.

Writing in the circuit in the first concrete example having such aconfiguration will now be described with reference to FIG. 14. FIG. 14is a diagram for explaining a write method used when conducting writinginto the memory transistor 10 ₁ connected to the word line WL1 and thebit line BL1 in the circuit of the first concrete example. Among the bitlines BL1, BL2 and BL3, 0 V is applied to the bit line BL1 connected tothe memory transistor to be written in, whereas the write inhibitvoltage is applied to other bit lines BL2 and BL3. Writing is conductedby using the method described in the first embodiment.

Second Concrete Example

A second concrete example shown in FIG. 15 is a circuit in a case wherecells which are adjacent to each other in the row direction do not sharea bit line. In other words, in the first concrete example shown in FIG.13, a bit line connected to the memory transistor 10 ₂ in the cell inthe first column and a bit line connected to the memory transistor 10 ₁in the cell in the second column are the same bit line BL2. In thesecond concrete example, a bit line connected to the memory transistor10 ₂ in the cell in the first column is the bit line BL2, whereas a bitline connected to the memory transistor 10 ₁ in the cell in the secondcolumn is the bit line BL3. A bit line connected to the memorytransistor 10 ₂ in the cell in the second column is a bit line BL4. Theconfiguration is the same as that in the first concrete example exceptthat cells which are adjacent in the row direction do not share a bitline.

Writing in the circuit in the second concrete example will now bedescribed with reference to FIG. 16. FIG. 16 is a diagram for explaininga write method used when conducting writing into the memory transistor10 ₁ connected to the word line WL1 and the bit line BL1. Selectivewriting is implemented by applying 0 V to the bit lines BL1 and BL2 andapplying the write inhibit voltage to the bit lines BL3 and BL4.

There are device requirements described hereafter for the cutofftransistor 20 in the present embodiment.

First, the gate insulation film in the cutoff transistor 20 mustwithstand the write inhibit voltage because in the write preventingmethod shown in FIG. 8 the gate insulation film in the cutoff transistor20 is subjected to the write inhibit voltage at its edge on the node 15side. Denoting a film thickness of the gate insulation film of thecutoff transistor 20 by T_(c), conditions required for the filmthickness T_(c) will now be found. Hereafter, every film thickness isrepresented by EOT (Equivalent Oxide Thickness). The equivalent oxidethickness T_(eq) is found according to the following Expression (1) byusing a physical film thickness T_(o) which can be measured by means ofTEM (Transmission Electron Microscopy) analysis or the like, adielectric constant ∈ of the insulation film, and a dielectric constant∈_(SiO2) of SIO₂.T _(eq) =T _(o)×∈_(SiO2)/∈  (1)

In the memory transistor, there are a lower limit of electric fieldE_(lim1) which is applied to the gate insulation film and which isrequired to write data, and an upper limit of electric field E_(lim2)which is applied to the gate insulation film and with which writing doesnot occur. Denoting the total sum of film thicknesses of the gateinsulation film of the memory transistor by T_(M), a write inhibitvoltage V_(inh) needs to satisfy a condition expressed by the followingExpression (2).V _(inh)≧(E _(lim1) −E _(lim2))×T _(M)  (2)Here, the total sum T_(M) of film thicknesses means the sum of a filmthickness of the tunnel film and a film thickness of the inter-electrodeinsulation film, in the case of an FG memory transistor. On the otherhand, in the case of the MONOS memory transistor, which employs aninsulation film such as a silicon nitride film to trap charges, T_(M)means the sum of a film thickness of the tunnel film, a film thicknessof the charge trap film, and a film thickness of the block insulationfilm.

When a write inhibit voltage V_(inh) is applied to the gate insulationfilm in the cutoff transistor, an electric field E_(C) is found by usingthe following Expression (3).E _(C) =V _(inh) /T _(C)  (3)

Denoting an electric field which causes the breakdown of the gateinsulation film by E_(BK), the electric field E_(C) must be less thanthe breakdown electric field E_(BK). Combining Expression (3) withExpression (2), therefore, the following Expression (4) is led.T _(C)≧(E _(lim1) −E _(lim2))×T _(M) /E _(BK)  (4)

In the general flash memory, a difference between the lower limit ofelectric field E_(lim1) and the upper limit of electric field E_(lim2)is approximately 5 MV/cm. As for a criterion of the breakdown electricfield E_(BK), a high voltage is applied to the gate insulation film inthe cutoff transistor only when writing into the memory is conducted,and this does not hold true during the operation of the logic switch. Anelectric field applied to the tunnel insulation film in the flash memoryat the time of writing is approximately 20 MV/cm. Setting this as thecriterion of the breakdown electric field E_(BK), it is found fromExpression (4) that the total sum T_(C) of the film thicknesses is atleast T_(M)/4.

Furthermore, the electric field applied to the gate insulation filmshould be less than 10 MV/cm to implement a transistor having higherreliability. Using this as the breakdown electric field E_(BK), it isrequired that the total sum T_(C) of the film thicknesses is at leastT_(M)/2.

If reliability equivalent to that of the ordinary logic transistor isrequired of the cutoff transistor, it is required from the foregoingdescription that the total sum T_(C) of the film thicknesses is at leastT_(M)/2. On the other hand, if only reliability equivalent to that ofthe flash memory transistor is required of the cutoff transistor, it isrequired that the total sum T_(C) of the film thicknesses is at leastT_(M)/4.

For ensuring high speed of the logic switch, the film thickness of thegate insulation film in the pass transistor is desired to be several nm.On the other hand, the total sum of the film thicknesses of the gateinsulation film in the memory transistor is approximately 15 nm. Becauseof the above-described requirement, therefore, the film thickness of thegate insulation film in the cutoff transistor is greater than that ofthe pass transistor. If different gate insulation films of three kindsare prepared for the memory transistor, the cutoff transistor, and thepass transistor, however, it is disadvantageous in respect of theprocess cost because of an increased number of times of lithography.

For reducing the cost, therefore, it is desirable to make the structureof the gate insulation film in the cutoff transistor the same as that inthe memory transistor. A logic switch in this case is shown in FIG. 17.The logic switch in a fourth example shown in FIG. 17 has aconfiguration obtained by replacing the cutoff transistor 20 with aflash memory transistor 20A in the logic switch in the first exampleshown in FIG. 2. As a result, a gate stack of the memory transistors 10₁ and 10 ₂ and a gate stack of the cutoff transistor 20A can befabricated in the same process. Therefore, it is possible to reduce thecost because of the process simplification. Furthermore, in the casewhere a plurality of transistors which differ in the configuration ofthe gate insulation film are prepared, it is necessary to provide alarge spacing between a transistor and another transistor due tolimitations of fabrication processes. In the case of the fourth exampleshown in FIG. 17, however, the gap becomes unnecessary and consequentlyit is possible to reduce the area of the chip.

As a second requirement for the cutoff transistor, the junction betweenthe source/drain and the channel must withstand the write inhibitvoltage. Here the terminal of the cutoff transistor 20 which isconnected to the node 15 is defined as source. If the cutoff transistor20 is n-type, its source is doped to the n-type and its channel is dopedto the p-type. Since the potential on the channel is equal to thesubstrate potential and is typically 0 V, a reverse bias which is equalto the write inhibit voltage in magnitude is applied across a pnjunction between the source and the channel. In general, the breakdownvoltage of a pn junction becomes smaller as the doping concentration inboth regions gets higher. In the cutoff transistor, therefore, a limitis imposed on an impurity concentration in the source or the channel.

First, the channel impurity concentration in the cutoff transistor willnow be discussed. By the way, in the present specification, an impurityconcentration is supposed to be an impurity concentration afteractivation. This impurity concentration can be measured by analysisusing, for example, an SSRM (Scanning Spread Resistance Microscope) orthe like. The impurity concentration in the channel is denoted byN_(CH), and it is supposed that a channel-source junction is an abruptjunction in which the source is doped with high concentration. Thenrelational Expression (5) holds true between the breakdown voltageV_(BK) and a maximum electric field E_(m) in the pn junction (see, forexample, Appl. Phys. Lett. 8, 111 (1966)).V _(BK)=(∈_(S) ×E _(m) ²)/(2×q×N _(CH))  (5)Here, ∈_(S) is a dielectric constant of silicon, and q is an elementaryelectric charge. Since the write inhibit voltage V_(inh) must be V_(BK)or below, the following Expression (6) holds true.N _(CH)≦(∈_(S) ×E _(m) ²)/(2×q×V _(inh))  (6)In addition, the Expression (6) can be rewritten by using Expression (2)as represented by the following Expression (7).N _(CH)≦(∈_(S) ×E _(m) ²)/(2×q×(E _(lim1) −E _(lim2))×T _(M))  (7)

In general flash memory, the difference between E_(lim1) and E_(lim2) isapproximately 5 MV/cm. Furthermore, the maximum electric field E_(m)when the breakdown of a junction occurs is generally approximately 2MV/cm. Therefore, the following Expression (8) is led as regards theimpurity concentration N_(CH).N _(CH)≦2×∈_(S)/(5×q×T _(M))  (8)For example, if T_(M)=15 nm, the impurity concentration N_(CH) must be1.7×10¹⁸ cm⁻³ or less.

Next, the impurity concentration in the source/drain of the cutofftransistor will be discussed. In the foregoing description, thenecessary condition of the impurity concentration in the channel hasbeen found supposing that the source of the cutoff transistor is dopedwith high concentration. As a matter of fact, however, the channelimpurity concentration N_(CH) cannot be made small immoderately in orderto prevent characteristics from being degraded by size shrinking. Forexample, if the gate length is 100 nm or less, an impurity concentrationof 1×10¹⁸ cm⁻³ or more is necessary as N_(CH). Instead, therefore, it isnecessary to make the impurity concentration N_(s) in the source low tosome degree.

When the write inhibit voltage V_(inh) is applied to an abrupt step pnjunction in which one impurity concentration is N_(CH) and the otherimpurity concentration is N_(S), the maximum electric field E_(m) in thepn junction is found as represented by the following Expression (9).E _(m)=((2×(φ+V _(inh))×q×N _(CH) ×N _(S))/(∈_(S)×(N _(CH) +N_(S)))^(1/2)  (9)

Here, φ is a built-in potential for the pn junction, and it isapproximately 1 V. Substituting E_(lim1)−E_(lim2)=5 MV/cm and T_(M)=15nm into Expression (2), V_(inh) is found to be 7.5 V. As for the maximumelectric field E_(m) when junction breakdown occurs, approximately 2MV/cm is its criterion. For example, if the impurity concentrationN_(CH) is in the first half of a 1×10¹⁸ cm⁻³ level, excess of theimpurity concentration N_(S) in the source over one hundred times theimpurity concentration N_(CH) in the channel causes the maximum electricfield E_(m) to begin to exceed 2 MV/cm. In other words, one hundredtimes of N_(CH) or less is a criterion of the impurity concentrationN_(S) for preventing the junction breakdown. In the general logictransistor, N_(S) has an impurity concentration of approximately 1×10²¹cm⁻³ or more. As compared with the general logic transistor, theimpurity concentration N_(S) in the source of the cutoff transistor mustbe made very small.

On the other hand, if the impurity concentration N_(S) in the source isless than the impurity concentration N_(CH) in the channel, the netpolarity of impurities in the source changes. Thus consequently theimpurity concentration N_(S) in the source needs to satisfy thecondition indicated by the following Expression (10).N _(CH) <N _(S) <N _(CH)×100  (10)

The foregoing description concerns the source of the cutoff transistor,i.e., the n-doped diffusion layer connected to the node 15. On the otherhand, on the drain side, the write inhibit voltage is not applied to thejunction between the drain and channel. As regards the impurityconcentration in the drain, therefore, it is not necessary to considerthe restriction as described above. For reducing the resistance betweenthe source and drain of the cutoff transistor, it is desired that theimpurity concentration in the drain is sufficiently high. As for theimpurity concentration in the source/drain of the cutoff transistor,therefore, the impurity concentration on the drain side should be madehigher as compared with that on the source side. When the resistancebetween the source and drain of the cutoff transistor is made small, thepotential on the gate in the pass transistor can be fixed more intenselyin the operation of the logic switch and consequently operation error ofthe pass transistor can be suppressed.

In writing into the memory transistor, a region between the source anddrain of the cutoff transistor subjected to the strongest voltage is thepn junction between the channel and the source. If a voltage equivalentto the write inhibit voltage is applied to the pn junction in thereverse direction, a depletion layer is formed on a boundary of the pnjunction. A width W_(D) of the depletion layer is represented by thefollowing Expression (11) using the impurity concentration N_(CH) in thechannel of the cutoff transistor, the impurity concentration N_(S) inthe source, and the write inhibit voltage V_(inh).W _(P)=((2×∈_(S)×(N _(CH) +N _(S))×(φ+V _(inh))/(q×N _(CH) ×N_(S)))^(1/2)  (11)

If the depletion layer generated on the source side is connected to thedrain, the cutoff transistor does not operate normally. Therefore, agate length L_(G) of the cutoff transistor must be greater than W_(D).Since the built in potential φ is approximately 1 V, the gate lengthL_(G) must satisfy a condition represented by Expression (12).L _(G)>((2×∈_(S)×(N _(CH) +N _(S))×(φ+V _(inh))/(q×N _(CH) ×N_(S)))^(1/2)  (12)Substituting φ=1 V and V_(inh)=7.5 V into Expression (12), Expression(13) is obtained.L _(G)>((17×∈_(S)×(N _(CH) +N _(S))/(q×N _(CH) ×N _(S)))^(1/2)  (13)For example, if N_(CH) is 2×10¹⁸ cm⁻³ and N_(s) is 2×10²⁰ cm⁻³, the gatelength L_(G) is found to be at least 75 nm.

First Comparative Example

A logic switch in a first comparative example according to the firstembodiment is shown in FIG. 18. The logic switch in the firstcomparative example has a configuration obtained by eliminating thecutoff transistor 20 in the logic switch in the first example shown inFIG. 2. In other words, the logic switch in the first comparativeexample includes two memory transistors 10 ₁ and 10 ₂ and one passtransistor 30. The drain of the memory transistor 10 ₁, the drain of thememory transistor 10 ₂ and the gate of the pass transistor 30 areconnected to a common node 15. In the logic switch in the comparativeexample, the power supply voltage is applied to one of the bit line BL1and the bit line BL2 and 0 V is applied to the other of them, at thetime of operation. The power supply voltage or 0 V is applied to thenode 15 connected to the gate of the pass transistor 30 on the basis ofinformation programmed for the memory transistors. As a result, on/offof the pass transistor 30 is changed over.

A method for writing data selectively into a memory transistor in thefirst comparative example will now be considered. For example, whenconducting writing into the memory transistor 10 ₁, i.e., when injectingelectrons into the charge trap film, a positive write voltage is appliedto the word line WL1. The write voltage is, for example, 20 V. At thesame time, 0 V is applied to the bit line BL1 and the bit line BL2, and0 V is applied to the word line WL2 as well. Thereupon, a channel isformed in the memory transistor 10 ₁ by the positive voltage applied tothe word line WL1, and the channel and the bit line BL1 are equal inpotential and 0 V. Because of a great potential difference between thechannel and the gate, electrons in the channel are injected into thecharge trap film beyond the tunnel film by the FN tunnel current at thistime. On the other hand, since the gate of the memory transistor 10 ₂ is0 V, writing into the memory transistor 10 ₂ is not conducted.

If the logic switches in the first comparative example shown in FIG. 18are arranged in an array form as cells, a plurality of memorytransistors share a word line. For implementing selective writing into amemory, therefore, a technique for preventing writing by contrivingconditions of voltages applied to bit lines even if a write voltage isapplied to a word line is necessary. It is now supposed that the cell inthe first comparison example shown in FIG. 18 is a cell where writing isnot conducted, i.e., an unselected cell. For preventing writing into thememory transistor 10 ₁ when a write voltage is applied to the word lineWL1, a write inhibit voltage is applied to the bit line BL1. Forexample, if the memory write voltage is 20 V, the write inhibit voltageis approximately 5 V. At this time, a channel is formed in the memorytransistor 10 ₁ in the same way as the selected cell. Since thepotential on the channel is 5 V, however, the potential differencebetween the channel and the gate is 15 V and thus injection of electronsdoes not occur.

In the write preventing method, however, the potential on the node 15connected to the gate of the pass transistor 30 is equal to thepotential on the bit line BL1, and it is, for example, 5 V. Forobtaining a high speed logic switch, a high-performance transistor isdemanded as the pass transistor. However, the gate insulation film ofthe high-performance transistor is as thin as several nm. If the writeinhibit voltage is applied to the gate of the pass transistor, there isa fear that the gate insulation film will be broken down. In the logicswitch in the first comparative example, therefore, the gate insulationfilm of the pass transistor need have a film thickness which is greatenough to prevent breakdown caused by the write inhibit voltage. As aresult, the speed of the logic switch falls.

Second Comparative Example

A programmable logic switch according to a second comparative example isshown in FIG. 19. The logic switch according to the second comparativeexample has a configuration obtained by eliminating the cutofftransistor and providing an access transistor 50 in the logic switchaccording to the first example shown in FIG. 2. By the way, in thesecond comparative example, drains of the memory transistors 10 ₁ and 10₂, the gate of the pass transistor 30, and a drain of the accesstransistor 50 are connected to a common node 16. Furthermore, gates ofboth the memory transistors 10 ₁ and 10 ₂ are connected to a common wordline WL.

In the logic switch in the second comparative example, the power supplyvoltage is applied to one of the bit line BL1 and the bit line BL2 and 0V is applied to the other of the bit line BL1 and the bit line BL2, atthe time of operation. The power supply voltage or 0 V is applied to thenode 16 connected to the gate of the pass transistor 30 on the basis ofinformation programmed for the memory transistors. As a result, on/offof the pass transistor 30 is changed over.

It is now supposed that data is to be written into a memory transistorselectively in the second comparative example shown in FIG. 19. Forexample, when conducting writing into the memory transistor 10 ₁, afirst write voltage is applied to the word line WL, a second writevoltage is applied to the bit line BL1, and 0 V is applied to the bitline BL2. Furthermore, the access transistor is turned on, and then 0 Vis applied to the access transistor 50 at its source. The first writevoltage is, for example, 10 V and the second write voltage is, forexample, 5 V. At this time, the memory transistor 10 ₁ operates in thesaturation region, and the channel pinch-off occurs on the bit line BL1side. As a result, hot-electrons having high energy are generated.Writing is implemented by injecting the hot-electrons into the chargetrap film in the memory transistor 10 ₁ by means of the gate voltage. Onthe other hand, in the memory transistor 10 ₂, there is no potentialdifference between the source/drain and consequently hot-electrons arenot generated and thus writing does not occur.

In the second comparative example, writing using hot-electrons isadopted for the memory programming. As compared with the case where theFN current is used, however, writing using hot-electrons isdisadvantageous in size shrinking of transistors in the channeldirection. In particular, it is known that the generation efficiency ofhot-electrons degrades if the gate length of a memory transistor becomesapproximately 100 nm or less. For implementing memory writing usinghot-electrons when the gate length is shrunk to, for example, 50 nm orless, therefore, it is necessary to strictly control the impurityprofile in, for example, the channel or source/drain. Therefore,increase of the development cost is necessarily caused. In addition, itis considered that an operation error caused by dispersion on theprocess is apt to occur.

According to the first embodiment and its examples, selective memorywriting is made possible and it is possible to prevent breakdown of thegate insulation film in the pass transistor at the time of writing andmake the gate insulation film thin, as described heretofore.Furthermore, since the FN current can be used for writing into a memory,the chip size can be made small without degrading the writecharacteristics, i.e., without hampering the write efficiency.

Second Embodiment

A logic switch according to a second embodiment is shown in FIG. 20. Thelogic switch according to the second embodiment has a configurationobtained by eliminating one of the two memories 10 ₁ and 10 ₂ andleaving the other as memory transistor 10 in the logic switch accordingto the first embodiment shown in FIG. 1.

Even if the potential on the node 15 changes during all operations suchas writing, erasing or other operations for the memory transistor 10, itis possible in the second embodiment to intercept the potential by thecutoff transistor 20 and prevent a high voltage from being applied tothe gate of the pass transistor 30, in the same way as the firstembodiment.

First Example

A logic switch according to a first example which uses a flash memorytransistor (referred to as memory transistor as well) as the memorytransistor 10 in the second embodiment is shown in FIG. 21. The memorytransistor 10 is formed in a well, and a terminal SUB for applying thesubstrate voltage is provided in the well.

Second Example

A logic switch according to a second example is shown in FIG. 22. Thelogic switch according to the second example has a configurationobtained by forming the memory transistor 10, and the cutoff transistor20 and the pass transistor 30 in different wells isolated by a deviceisolation region in the first example shown in FIG. 21. Therefore, aterminal SUB1 for applying a substrate bias is provided in a well inwhich the memory transistor 10 is formed, and a terminal SUB2 forapplying a substrate bias is provided in a well in which the cutofftransistor 20 and the pass transistor 30 are formed. Owing to such aconfiguration, the substrate bias can be applied to the memorytransistor 10 independently of the cutoff transistor 20 and the passtransistor 30.

(Write Method)

A program method (write method) of a memory in the logic switchaccording to the second embodiment will now be described with referenceto FIG. 23. If it is desired to write data selectively into the memorytransistor 10, a write voltage is applied to the word line WL1. Thewrite voltage is, for example, 20 V. 0 V is applied to a word lineconnected to the gate of the memory transistor to be not written in.Furthermore, 0 V is applied to the bit line BL1. At this time, a channelis formed in the memory transistor 10 into which writing should beconducted selectively, and electrons are injected from the channel intothe charge trap film by an FN current.

(Write Preventing Method)

In the case where a plurality of logic switches are arranged in anarray, a plurality of memory transistors share a word line. If a writevoltage 20 V is applied to a word line connected to the gate of a memorytransistor to be written in, therefore, the 20 V is also applied to agate of a memory transistor which is other than the memory transistor tobe written in and which is connected to the word line, i.e., a gate of amemory transistor to be not written in. In order to implement selectivewriting, therefore, a write inhibit voltage of 5 V is applied to the bitline BL1 connected to the memory transistor 10 to be not written in asshown in FIG. 24 and consequently unexpected false error into a memorytransistor to be not written in is prevented. In the memory transistor10 to be not written in, the voltage of 20 V is applied to its gate andconsequently a channel is formed. Since a potential on the channel is 5V which is equal to the potential on the bit line BL1 and a potentialdifference between the channel and the gate is 15 V, however, writingerror does not occur. At this time, the potential on the node 15 is also5 V. If the cutoff transistor 20 is brought into the off-state byadjusting the potential on the control line CL connected to the gate ofthe cutoff transistor 20, however, 5 V is not applied to the gate of thepass transistor 30. In FIG. 24, the voltage applied to the control lineCL is 0 V. However, the voltage applied to the control line CL may notbe 0 V as long as it is lower than a threshold voltage of the cutofftransistor 20.

(Erase Method)

A method for erasing data in memories in the logic switch according tothe second embodiment will now be described with reference to FIGS. 25to 27.

FIG. 25 shows a first concrete example of the erase method. An erasevoltage is applied to the word line WL1 in a state in which 0 V isapplied to the terminal SUB as the substrate bias and the potential onthe bit line BL1 is made to be 0 V. At this time, the erase voltage isnegative in sign and is, for example, −20 V. A second concrete exampleof the erase method is shown in FIG. 26. In the erase method of thesecond concrete example shown in FIG. 26, a positive erase voltage of,for example, 20 V is applied to the terminal SUB in a state in which thepotential on the word line WL1 is brought to 0 V. At this time, the bitline BL1 should be kept in the floating state, or should be suppliedwith a voltage which is at least the voltage applied to the terminalSUB. In the case of the second concrete example shown in FIG. 26, anegative voltage is not necessary and consequently a power supply fornegative voltage may not be provided and an advantage that the area canbe made small is obtained. If the well for the memory transistor iscommon to the well for the pass transistor, however, the substrate biasis output from the pass transistor 30 via the source/drain of the passtransistor 30 by applying 20 V as the substrate bias. In general, it isconsidered that an output of the pass transistor 30 is connected to, forexample, an input of an inverter. If the voltage of 20 V is applied tothe input of the inverter, then a problem that gate breakdown of thetransistor in the inverter might occur is posed. This problem can besolved by adopting a configuration capable of applying differentsubstrate biases to the memory transistor 10 and the pass transistor 30respectively, i.e., a configuration in a third example. If in this case,for example, the substrate bias of the pass transistor 30 is set equalto 0 V as indicated in an erase method of a third concrete example shownin FIG. 27, the problem can be solved.

On the other hand, in the erase method in the first concrete exampleshown in FIG. 25, the substrate bias applied to the terminal SUB is setequal to 0 V and consequently a high voltage is not output from the passtransistor 30. Furthermore, even if the potential on the node 15 ismodulated in the negative direction by a negative voltage applied to theword line WL1, the substrate bias of 0 V is applied via the source/drainof the memory transistor 10, and the potential on the node 15 gets equalto 0 V swiftly.

(Operation of Logic Switch)

An example of a voltage applying condition in a case where theprogrammable logic switch is made to operate on the basis of informationwritten into a memory is shown in FIG. 28. It is now supposed that thememory transistor 10 is programmed. A read voltage Vread is applied tothe word line WL1. The read voltage Vread is an arbitrary voltage whichis greater than a threshold voltage of the memory transistor 10 in theerase state and which is less than a threshold voltage of the memorytransistor 10 in the write state. Furthermore, a voltage Vpass which isat least the threshold voltage of the cutoff transistor 20 is applied tothe control line CL to electrically connect the gate of the passtransistor 30 to the node 15. The power supply voltage VDD is applied tothe bit line BL1. In response to the program state of the memorytransistor, the gate of the pass transistor 30 is connected to the powersupply voltage VDD or brought into the floating state, and the passtransistor 30 is brought into the on-state or off-state.

In general, even if the power supply is cut off, data are not lost inthe nonvolatile programmable logic switch. Therefore, it is possible toimplement the power gating technique which reduces the power consumptionof the whole chip by cutting off the power supply for regions which arenot being used. In general, a transistor for signal interception isprovided between the power supply and the memory transistors to preventthe power supply voltage from being applied to the memory transistor 10.In this case, however, additional transistors for cutting off the powersupply are necessary.

In the second embodiment, it is possible to prevent the power supplyvoltage from being applied to the gate of the pass transistor 30 byturning off the cutoff transistor 20 in regions which are not beingused. As a result, it is possible to exclude power consumption caused bya gate leakage current of the pass transistor 30 and it becomes possibleto yield an effect equivalent to that of the power gating.

(Logic Switch Arranged in Array Form)

A concrete example in a case where the logic switches according to thesecond embodiment are arranged in an array form as cells will now bedescribed with reference to FIGS. 29 and 30.

FIG. 29 is a circuit diagram showing a concrete example. A circuit inthe concrete example shown in FIG. 29 includes cells M_(ij) (i, j=1, 2)arranged in two rows by two columns, and each cell is, for example, thelogic switch in the first example shown in FIG. 21.

In the cells M₁₁ and M₁₂ in a first row, the memory transistor 10 isconnected at its gate to the word line WL1, and the cutoff transistor 20is connected at its gate to a control line CL1.

In the cells M₂₁ and M₂₂ in a second row, the memory transistor 10 isconnected at its gate to a word line WL2, and the cutoff transistor 20is connected at its gate to a control line CL2.

In the cells M₁₁ and M₂₁ in a first column, the memory transistor 10 isconnected at one of its source/drain to the bit line BL1. Furthermore,the path transistor 30 is connected at one of its source/drain to aninterconnection Y1 disposed in the column direction, and connected atthe other of its source/drain to an interconnection X1 or aninterconnection X2 disposed in the row direction.

In the cells M₁₂ and M₂₂ in a second column, the memory transistor 10 isconnected at one of its source/drain to the bit line BL2. Furthermore,the path transistor 30 is connected at one of its source/drain to aninterconnection Y2 disposed in the column direction, and connected atthe other of its source/drain to the interconnection X1 or theinterconnection X2 disposed in the row direction.

Writing in the circuit in the concrete example having such aconfiguration will now be described with reference to FIG. 30. FIG. 30is a diagram for explaining a write method used when conducting writinginto the memory transistor 10 connected to the word line WL1 and the bitline BL1 in the circuit of the concrete example. Among the bit lines BL1and BL2, 0 V is applied to the bit line BL1 connected to the memorytransistor to be written in, whereas the write inhibit voltage isapplied to the other bit line BL2. Writing is conducted by using themethod described in the second embodiment.

A logic switch according to a third example in the second embodiment isshown in FIG. 31. The logic switch according to the third example has aconfiguration obtained by replacing the cutoff transistor 20 with aflash memory transistor 20A in the logic switch in the first exampleshown in FIG. 21. As a result, a gate stack of the memory transistor 10and a gate stack of the cutoff transistor 20A can be fabricated in thesame process. Therefore, it becomes possible to reduce the cost becauseof the process simplification.

In the second embodiment as well, requirements for the cutoff transistorare the same as those in the case of the first embodiment.

According to the second embodiment and its examples as well, selectivememory writing is made possible and it is possible to prevent breakdownof the gate insulation film in the pass transistor at the time ofwriting and make the gate insulation film thin, in the same way as thefirst embodiment. Furthermore, since the FN current can be used forwriting into a memory, the chip size can be made small without degradingthe write characteristics, i.e., without hampering the write efficiency.

Third Embodiment

An FPGA according to a third embodiment will be described with referenceto FIGS. 32( a) to 32(d). FIG. 32( a) shows an FPGA 100 of thisembodiment, which includes a plurality of basic tiles 102 arranged in anarray form, and input and output units I/O arranged around the array ofthe basic tiles 102. Each of the basic tiles 102 includes a logic block(hereinafter also referred to as “LB”) 104 and a switch block(hereinafter also referred to as “SB”) 106. Each logic block 104 has amultiplexer 110 or 112 as shown in FIG. 32( b) or 32(c), to achieve alogical function. The multiplexer 110 shown in FIG. 32( b) selects, asits output signal, at least one of output signals from a plurality ofmemories based on input signals IN1, IN2, . . . . The multiplexer 112shown in FIG. 32( c) selects, as its output signal, at least one ofinput signals IN1, IN2, . . . based on signals from memories. As shownin FIG. 32( d), the switch block 106 has a plurality of switches 114 a,114 b each turning on/off based on information stored in a memory, andhas a function of changing the combination of the wiring connectionusing the switches. Thus, the logic block 104 and the switch block 106each have memories for storing information. By rewriting the informationstored in these memories, the entire FPGA achieved a desired logic.Information to be stored in the memories is externally inputted by meansof the input and output units I/O. As the multiplexer and the memoriesin the logic block 104, the programmable logic switches of the first andthe second embodiments are used, and as the switches and the memories ofthe switch block 106, the programmable logic switches of the first andthe second embodiments are used.

As in the cases of the first and the second embodiments, the FPGA of thethird embodiment thus configured prevents the breakage of the gateinsulating film of the pass transistor during the selective writing ofmemories, and makes it possible to reduce the thickness of the gateinsulating film of the pass transistor. Furthermore, it is possible toobtain an FPGA, in which the write efficiency is not impaired byminiaturizing memories.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and systems describedherein can be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein can be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

The invention claimed is:
 1. A nonvolatile programmable logic switchcomprising first and second cells, each of the first and second cellscomprising: a first memory having a first terminal, a second terminal,and a third terminal which receives a control signal to control a memorystate, the first memory being a first memory transistor having a gatestructure formed by stacking a first insulation film, a charge trapfilm, a second insulation film, and a gate electrode, a source and adrain of the first memory transistor being the first and secondterminal, and the gate electrode being the third terminal; a firsttransistor connected at one of source/drain thereof to the secondterminal; and a second transistor connected at a gate thereof to theother of the source/drain of the first transistor, the third terminal ofthe first memory in the first cell and the third terminal of the firstmemory in the second cell being connected in common, and when conductingwriting into the first memory in the first cell, the third terminalsbeing connected to a write power supply which generates a write voltage,the first terminal of the first memory in the first cell being connectedto a ground power supply which generates a ground voltage, and the firstterminal of the first memory in the second cell being connected to awrite inhibit power supply which generates a write inhibit voltage, thewrite inhibit voltage being between the ground voltage and the writevoltage.
 2. The switch according to claim 1, wherein denoting a totalsum of film thicknesses of an insulation film in the gate structure ofthe first memory transistor by T_(M), a total sum T_(C) of filmthicknesses of an insulation film in a gate structure of the firsttransistor satisfies a relationT _(C) ≧T _(M)/4.
 3. The switch according to claim 1, wherein denoting atotal sum of film thicknesses of an insulation film in the gatestructure of the first memory transistor by T_(M), a total sum T_(C) offilm thicknesses of an insulation film in a gate structure of the firsttransistor satisfies a relationT _(C) ≧T _(M)/2.
 4. The switch according to claim 1, wherein denoting atotal sum of film thicknesses of an insulation film in the gatestructure of the first memory transistor by T_(M), a dielectric constantof silicon by ∈_(S), and an elementary electric charge by q, an impurityconcentration N_(CH) in a channel in the first transistor satisfies arelationN _(CH)≦2×∈_(S)/(5×q×T _(M)).
 5. The switch according to claim 1,wherein denoting an impurity concentration in a channel in the firsttransistor by N_(CH), a maximum impurity concentration N_(S) in thesource/drain of the first transistor connected to the second terminalsatisfies a relationN _(CH) <N _(S) <N _(CH)×100.
 6. The switch according to claim 1,wherein a maximum impurity concentration in the source/drain of thefirst transistor connected to the gate of the second transistor isgreater than a maximum impurity concentration in the source/drain of thefirst transistor connected to the second terminal.
 7. The switchaccording to claim 1, wherein denoting an impurity concentration in achannel in the first transistor by N_(CH), a maximum impurityconcentration in the source/drain of the first transistor connected tothe second terminal by N_(S), a dielectric constant of silicon by ∈_(S),and an elementary electric charge by q, a gate length L_(G) of the firsttransistor satisfies a relationL _(G)>((17×∈_(S)×(N _(CH) +N _(S))/(q×N _(CH) ×N _(S)))^(1/2).
 8. Theswitch according to claim 1, wherein the first memory transistor isformed in a first well, the first transistor and the second transistorare formed in a second well different from the first well, and each ofthe first and second wells comprises an electrode to apply a substratebias.
 9. The switch according to claim 1, wherein each of the first andsecond cells comprises a second memory, and the second memory comprisesa fourth terminal, a fifth terminal connected to the second terminal,and a sixth terminal which receives a control signal to control a memorystate, the second memory being a second memory transistor having a gatestructure formed by stacking a first insulation film, a charge trapfilm, a second insulation film, and a gate electrode, a source and adrain of the second memory transistor being the fourth and fifthterminal, and the gate electrode being the sixth terminal, the sixthterminal of the second memory in the first cell and the sixth terminalof the second memory in the second cell being connected in common. 10.The switch according to claim 9, wherein the first and second memorytransistors are formed in a first well, the first transistor and thesecond transistor are formed in a second well different from the firstwell, and each of the first and second wells comprises an electrode toapply a substrate bias.
 11. The switch according to claim 1, wherein thefirst transistor is a memory transistor having a gate structure formedby stacking a first insulation film, a charge trap film, a secondinsulation film, and a gate electrode.
 12. The switch according to claim1, wherein the charge trap film of the first memory transistor is a filmincluding silicon nitride.
 13. The switch according to claim 9, whereinthe charge trap film of each of the first and second memory transistorsis a film including silicon nitride.
 14. The switch according to claim1, wherein the first memory transistor, the first transistor and thesecond transistor are formed in a first well in which an electrode forapplying substrate bias is formed.
 15. The switch according to claim 14,wherein when conducting erasing into the first memory transistor in thefirst cell, the third terminals are connected to an erase power supplywhich generates a negative erase voltage, and the first well isconnected to a ground power supply.
 16. The switch according to claim 8,wherein when conducting erasing into the first memory transistor in thefirst cell, the third terminals are connected to a ground power supply,and the first well is connected to an erase power supply which generatesa positive erase voltage.
 17. The switch according to claim 1, whereinwhen controlling on/off of the second transistor, after the first memoryis set to be a writing state or an erasing state, the first terminal isconnected to a first power supply which generates a first power supplyvoltage, and a gate of the first transistor is connected to a firstcontrol power supply which generates a control supply voltage.
 18. Theswitch according to claim 9, wherein when controlling on/off of thesecond transistor, after the first memory is set to be a writing stateand the second memory is set to be an erasing state, one of the firstand fourth terminals is connected to a first power supply whichgenerates a first power supply voltage, the other of the first andfourth terminals is connected to a ground power supply, and a gate ofthe first transistor is connected to a first control power supply whichgenerates a control supply voltage.
 19. A nonvolatile programmable logicdevice comprising a plurality of wirings and a connection unitconfigured to switch connection/disconnection of the wirings, theconnection unit comprising one or more programmable logic switches, eachprogrammable logic switch comprising first and second cells, each of thefirst and second cells comprising: a first memory having a firstterminal, a second terminal, and a third terminal which receives acontrol signal to control a memory state, the first memory being a firstmemory transistor having a gate structure formed by stacking a firstinsulation film, a charge trap film, a second insulation film, and agate electrode, a source and a drain of the first memory transistorbeing the first and second terminal, and the gate electrode being thethird terminal; a first transistor connected at one of source/drainthereof to the second terminal; and a second transistor connected at agate thereof to the other of the source/drain of the first transistor,the third terminal of the first memory in the first cell and the thirdterminal of the first memory in the second cell being connected incommon, and when conducting writing into the first memory in the firstcell, the third terminals being connected to a write power supply whichgenerates a write voltage, the first terminal of the first memory in thefirst cell being connected to a ground power supply which generates aground voltage, and the first terminal of the first memory in the secondcell being connected to a write inhibit power supply which generates awrite inhibit voltage, the write inhibit voltage being between theground voltage and the write voltage.
 20. A nonvolatile programmablelogic device comprising a plurality of wirings and a connection unitconfigured to switch connection/disconnection of the wirings, theconnection unit comprising one or more programmable logic switches, eachprogrammable logic switch comprising first and second cells, each of thefirst and second cells comprising: a first memory having a firstterminal, a second terminal, and a third terminal which receives acontrol signal to control a memory state, the first memory being a firstmemory transistor having a gate structure formed by stacking a firstinsulation film, a charge trap film, a second insulation film, and agate electrode, a source and a drain of the first memory transistorbeing the first and second terminal, and the gate electrode being thethird terminal; a first transistor connected at one of source/drainthereof to the second terminal; a second transistor connected at a gatethereof to the other of the source/drain of the first transistor; and asecond memory, having a fourth terminal, a fifth terminal connected tothe second terminal, and a sixth terminal which receives a controlsignal to control a memory state, the second memory being a secondmemory transistor having a gate structure formed by stacking a firstinsulation film, a charge trap film, a second insulation film, and agate electrode, a source and a drain of the second memory transistorbeing the fourth and fifth terminal, and the gate electrode being thesixth terminal, the third terminal of the first memory in the first celland the third terminal of the first memory in the second cell beingconnected in common, the sixth terminal of the second memory in thefirst cell and the sixth terminal of the second memory in the secondcell being connected in common, and when conducting writing into thefirst memory in the first cell, the third terminals being connected to awrite power supply which generates a write voltage, the first terminalof the first memory in the first cell being connected to a ground powersupply which generates a ground voltage, and the first terminal of thefirst memory in the second cell being connected to a write inhibit powersupply which generates a write inhibit voltage, the write inhibitvoltage being between the ground voltage and the write voltage.
 21. Theswitch according to claim 1, wherein the first memory transistor is afloating gate transistor.
 22. The switch according to claim 1, whereinthe first memory transistor is a metal-oxide-nitride-oxide-semiconductortransistor.